1. Field of the Invention
The present invention relates to method and apparatus for protecting transistors used in chip interface circuits, and more particularly, to the protection of transistors used in CMOS transceiver receive and transmit circuitry.
2. Related Art
In modern submicron CMOS processes, minimum transistor dimensions have progressively become smaller over the years. This allows a faster operation, as well as the ability to integrate more functions on a chip. Transistor supply voltages have also been reduced, to maintain acceptable reliability of sub-micron transistors. However, there are still voltage level standards external to the chip that operate at higher voltages. Many legacy systems still work on 5V and 3.3V, although on-chip circuitry is required to work at 1.2V or 2.5V. The interface between the internal chip transistors and the external circuitry that operate at higher voltages is often a problem due to the need to ensure that the internal chip transistors at the interface do not fail due to the higher voltages.
Also, in certain wired communication standards, there is capability to make physical ‘hot pluggable’ connections. The reliability requirements for these interfaces specify a certain over-voltage and under-voltage limit that the devices there can tolerate. If these devices are implemented using CMOS transistors, they are subject to various failure mechanisms when a larger-than-foundry-specified maximum voltage is applied. One such failure mechanism is Time Dependent Dielectric Breakdown (TDDB), where, if a large voltage is applied at a gate of a CMOS device, the insulating properties of the silicon dioxide in the CMOS gate wear out, leading to a formation of a conducting path between the gate and the substrate. This then affects the gate-controlled conductivity properties of the transistor, causing circuit failure.
Another failure mechanism is hot carrier damage, where a transistor that is turned on is subjected to a drain-to-source voltage that is larger than the specified maximum. This occurs when a large electric field in the pinched off region causes channel carriers to collide with crystal atoms and to produce electron-hole pairs. These electrons can be scattered toward the gate oxide interface, degrading transistor transconductance.
A common solution to the problem of protecting input and output devices is to put external diode clamps on these inputs or outputs. When an overvoltage condition occurs, these diodes turn on and provide a high conductance current path which is able to clamp the voltage typically to VDD+Vd where VDD is the supply voltage and Vd is the diode threshold voltage. However, this form of protection requires additional external diodes, which increases cost and introduces capacitive parastitics that can degrade high frequency operation. Also, this solution does not solve the problem of interfacing to 5V or 3V systems when the internal chip circuitry is operating at, for example, 2.5V.
There are conventional approaches that address the 3V to 5V interface problem. One such scheme is described in Takahashi et al., 3.3V–5V Compatible I/O Circuit Without Thick Gate Oxide, IEEE 1992 Custom Integrated Circuit Conference. This scheme requires additional technology processing steps to create an intrinsic type PMOS and depletion type PMOS transistors. Pelgrom et al., A 3/5 V Compatible I/O Buffer, IEEE Journal of Solid State Circuits, Vol. 30, No. 7, July 1995, describe circuit techniques that are more suited for output drivers of the complimentary CMOS push-pull type, and not for high frequency output drivers of the current steering type. It is also more suited for low frequency operation as large cascode protection circuits are needed. Also, it does not have a protection scheme for undervoltage stress conditions.
In the case of the high speed serial transmitter outputs, a current steering circuit with resistive termination is typically used as the output driver. This current steering circuit is driven by a pre-driver which is conventionally a differential pair voltage buffer, also known as a current mode logic (CML) buffer. A conventional steering circuit 102 and a CML pre-driver 101 are shown in FIG. 1.
Referring to FIG. 1, the operation of the circuit is as follows: when a large differential input voltage is applied at Vip and Vin, a differential transistor pair of M101 and M102 steers a current IS from current source transistor M106 to either resistor R119 or R120, depending on the polarity of Vip and Vin. The steered current IS determines the output voltages of the pre-driver 101 at nodes Pre_von and Pre_vop.
The voltages at Pre_von and Pre_vop bias an input differential pair of PMOS transistors M120 and M121. If Pre_vop is high (at VDDP) and Pre_von is low (at VDDP−IxR), the transistor M121 will turn on, and current from M126 will flow into resistor R103 and build up a voltage at outp. Note that VDDP in FIG. 1 refers to 2.5V and VDDO refers to 3.3V.
Note that the voltage supply of the pre-driver 101 could have been connected to VDDO instead of VDDP, but because the inputs Vip and Vin are driven to 0V at times, this would have caused a gate-to-drain voltage at transistors M101 and M102 of 3.3V.
The conventional output stage driver of FIG. 1 suffers from several disadvantages:
In the event of a 5V being shorted to outp, when Pre_von is VDDP−IxR, the voltage across the gate and source of transistor M321 is 5V−(VDDP−IxR)=3.9V, which exceeds the typical specification for maximum gate to source voltage. In this example VDDP=2.5V and IxR=1.4V.
It is possible, due to power supply start up sequencing, or due to different voltage regulator start up times on the application board where the chip is being used, that certain supply voltages may be available sooner than others. For example, if VDDO (3.3V) is available and stable, but VDDP (2.5V) is not yet available, Pre_vop and Pre_von would be 0V, and if outp and outn is shorted to 5V, a full 5V appears across the drain and gate of transistors M120 and M121.
Also, in the event that the outputs outp and outn are shorted to 5V, the current that flows through the internal termination resistors R103 and R104, which are typically 45 ohms, is greater than 100 mA. This can cause electron migration failure if the number of vias and contacts and the metal widths used to connect outp to the resistors, as well as resistor widths, are insufficient. A thicker metal and resistor width for this signal would also mean greater area requirements, and hence increased cost.
Accordingly, there is a need in the art for a method and apparatus for on-chip protection of receive input and output driver circuitry that overcomes these disadvantages and is suitable for high frequency serial transceivers.